1. Field of the Invention
The present invention relates in general to a data transfer system and in particular to high frequency transfer of data between a data source and a data sink. Still more particularly, the present invention relates to a method and system for processing data received at the data sink over a wide range of bus cycles such that the data is accessible to the data sink at a controllable predetermined time.
2. Description of the Related Art
In transferring data from a data source which supplies data to a data sink which receives data, it is typically preferred that the speed of data transfer is as fast as possible. Factors that typically limit the speed of data transfer are the latency of the interface between the data source and the data sink and the requirements of cycle synchronization and deterministic transfer of data.
The latency of the interface between the data source and the data sink represents the time required for data to pass from the data source to the data sink. In determining the latency of an interface, typically the worst case slow path is analyzed. The worst case slow path determines the longest time that data may take to pass from the data source to the data sink. Several factors adding time to the worst case slow path may be the process time of the data source, high temperatures, low voltage, and the clock skew between the data source and the data sink. Additionally, in determining the latency of the interface, typically, the best case fast path is analyzed. The best case fast path determines the shortest time that data may take to pass from the data source to the data sink. By determining both the fast path and the slow path, a range of time during which the data can be expected to arrive at the data sink may be determined.
Cycle synchronization requires that, depending upon the bus cycle during which the data is transmitted from the data source, there is a specified bus cycle during which the data will be received at the data sink. For example, if data is transmitted at a first bus cycle, cycle synchronization for the system may specify that the data must be received at the data sink during a second bus cycle. Thereby, if the data is not received at the data sink until a third bus cycle, cycle synchronization is not maintained.
Deterministic transfer of data requires that the data will be available at the data sink for use or storage at a predetermined bus cycle. The predetermined cycle during which the data is available is typically at least one bus cycle after the bus cycle during which the data is received.
Deterministic transfer of data and cycle synchronization are crucial in a data transfer system in order to maintain the complex structure and orderly execution of instructions. In most cases, data malfunctions result if the data is received at the data sink before or after the bus cycle during which the data is expected.
Referring now to FIG. 1, a prior art data transfer system timing diagram is depicted wherein the bus cycle time is longer than the worst case latency. A data source bus clock is illustrated at reference numeral 200 where a first complete cycle of the data source bus clock is between time=0 and time=target cycle time and where the data is expected to be deterministically available at the bus cycle after the target cycle time. Data source data is depicted at reference numeral 202 which provides the data for the data sink to receive. The first data (a) received at the data sink is illustrated at reference numeral 204 arriving within the bus cycle that the data is transmitted, at a period of time after being transmitted. The period of time between when the first data (a) is transmitted at reference numeral 202 and received at reference numeral 204 is the latency across the interface. Second data (b) is transmitted during the second bus cycle at reference numeral 202 and received at reference numeral 204 during the second bus cycle after a period of time equal to the latency of the interface. A data sink local clock, which is at the same frequency and phase as the data source bus clock, is depicted at reference numeral 206. At the rising edge of the data sink local clock at time=target cycle time, the first data (a) becomes accessible at the data sink as illustrated at reference numeral 208. Thereby, if a new data element is transmitted, the data is guaranteed to be received during the bus cycle that the data is transmitted and accessible at the next bus cycle for use or storage at the data sink.
The prior art data transfer system depicted in FIG. 1 maintains cycle synchronization by always receiving data at the bus cycle during which the data is transmitted. Deterministic transfer is maintained because the data is always available at the data sink the bus cycle after the data is received.
However, while the prior art data transfer system maintains the requirements of cycle synchronization and deterministic transfer of data, the speed of transfer of each data element to the data sink is limited by the worse case latency time.
The need to increase the speed of data transfers between functional units is driving the development of improved methods of data transfer where it is contemplated that data may arrive over a range of bus cycles, and that interface latency exceeds bus cycle time.
A need exists for a method and system which permits high speed data transfer and maintains deterministic data transfer and cycle synchronization while allowing data to arrive over a range of bus cycles.
It is therefore one object of the present invention to provide a data transfer system.
It is another object of the present invention to provide high frequency transfer of data between a data source and a data sink.
It is yet another object of the present invention to provide an improved method and system for shifting data received at the data sink over a wide range of bus cycles such that the data is accessible to the functional unit at a controllable predetermined time.
The foregoing objects are achieved as is now described. A method and system of the present invention may be utilized to transfer data between the data source and the data sink. Both the data source and data sink include clocks which are synchronized to a common clock. A buffer is provided at the data sink and this buffer is utilized to received data from the data source. A control circuit is provided at the data sink and this control circuit receives a bus clock signal from the data source. An N segment dynamic shift register is provided which includes at least two segments. A selectable shift control is provided for passing the data through an M segment subset of the N segment shift register, where M is less than N. Additionally, the length of the M segment subset is determined by the phase of a clock within the data sink at the time which the bus clock signal from the data source is received at the data sink. By selectively passing the data through an M segment subset of the N segment shift register,-the data is accessible at the data sink at a controllable predetermined time.
The above as well as additional objects, features and advantages of the present invention will become apparent in the following written description.